1. Field of the Invention
The present invention relates to data processing apparatuses configured to generate an output frequency signal. More particularly, this invention relates to such oscillators that are configured to consume very little power.
2. Description of the Prior Art
It is known in the field of data processing apparatuses to provide an oscillator to generate an output frequency signal having a characteristic frequency. For example, one typical implementation is a sequence of an odd number of inverters having a feedback path from the output of the last inverter to the input of the first inverter. In such a ring oscillator, it is known that the output frequency FOSC is given by FOSC=i/(C.ΔV.N), where N is the number of inverter stages, ΔV is the voltage swing, C is the load and i is the driving current drawn by the ring oscillator. Accordingly, the output frequency of the signal generated by the ring oscillator can be controlled by the provision of an appropriate drive current.
A problem arises however in the implementation of such devices as the process technologies for integrated circuit manufacture become ever smaller. This is because at “sub-nanometer” process technologies (process nodes below 100 nm), the gain and leakage of the MOS devices is so high that a traditional ring oscillator with inverter stages becomes impractical. For example, a 15 stage ring oscillator produced at the nm process node runs at 11 GHz and burns several mille-Amps (mA) of current. Not only is this output frequency impractically high for typical implementation purposes, but further the current drawn is also undesirably high, in particular in the context of integrated circuits provided within low power (e.g. portable) devices.
Previously provided oscillator designs are described in: “Frequency Synthesizer Design In CMOS”, Milan Savić, Miljan Nikolić, Dragi{hacek over (s)}a Milovanović, FProc. 51st ETRAN Conference, Herceg Novi—Igalo, Jun. 4-8, 2007; “Design of a Ring-Oscillator with a Wide Tuning Range in 0.13 μm CMOS for the use in Global Navigation Satellite Systems”, S. Joeres, A. Kruth, O. Meike, G. Ordu, S. Sappok, R. Wunderlich and S. Heinen, Institute for Semiconductor Electronics, RWTH Aachen University, Germany; “A variable delay line PLL for CPU-coprocessor synchronization”, Johnson, M. G. and Hudson, E. L., IEEE Journal of Solid-State Circuits, October 1988, Vol. 23, No. 5, pp. 1218-1223; “An Ultra-Low-Power and Portable Digitally Controlled Oscillator for SoC Applications”, Duo Sheng; Ching-Che Chung; Chen-Yi Lee, IEEE Transactions on Circuits and Systems II: Express Briefs, November 2007, Vol. 54, No. 11, pp. 954-958; and “Linear Current Starved Delay Element”, Goran S. Jovanović and Mile K. Stoj{hacek over (c)}ev, Faculty of Electronic Engineering, Beogradska 14, 18000 Ni{hacek over (s)}, Serbia and Montenegro.
It would be desirable to provide an improved technique for the generation of an output frequency signal, in particular which would allow the generation of frequencies in a useful range, with modest power consumption, in an integrated circuit manufactured at contemporary (sub-nanometer) process nodes.